1. Field of the Invention
The invention relates to a magnetic random access memory for storing information of “1” or “0” by utilizing the magneto-resistive effects.
2. Description of the Related Art
A Magnetic Random Access Memory (MRAM) is a storage device for storing information of “1” or “0” by utilizing the magneto-resistive effects. Recently, many companies have started developments of the MRAM as one of candidates of universal storage devices combining non-volatility, a high integration density, high reliability, low power-dissipation, and high-speed operations.
As the magneto-resistive effects, there are two known effects of the Giant Magneto-Resistive (GMR) effect and the Tunnel Magneto-Resistive (TMR) effect. An element which exhibits the GMR effect utilizes an effect that the resistance of a conductor sandwiched between two ferromagnetic layers varies in accordance with spin alignment of these upper and lower ferromagnetic layers. The MR ratio, which indicates a ratio of the variation in magnetic resistance value, however, is as low as about 10%, so that a read-out signal for stored information is small. Therefore, the most critical problem in implementation of an MRAM has been to preserve a read-out margin, thus persuading the industries of insufficient practicability of the MRAM.
One example of an element which exhibits the TMR effect, on the other hand, is a Magnetic Tunnel Junction (MTJ) element which has a stack structure composed of two ferromagnetic layers and an insulation film sandwiched between these two metal ferromagnetic layers and utilizes a variation in magnetic resistance owing to the spin polarization tunnel effect. The MTJ element exhibits the maximum tunneling probability between the two magnetic layers via the tunnel insulation film therebetween when the upper and lower ferromagnetic layers are parallel to each other in spin alignment, thus resulting in the minimum resistance of the tunnel insulation film. When they are anti-parallel to each other in spin alignment, on the other hand, that tunnel probability is minimized, thus maximizing the resistance of the tunnel insulation film.
To implement these two spin states, either one of the above-mentioned two magnetic films is fixed in magnetization direction, to avoid an influence of external magnetization. This layer is generally referred to as a PIN layer. The other magnetic film can be programmed so that its magnetization direction may be parallel or anti-parallel to that of the PIN layer in accordance with the direction of a magnetic field applied thereon. This layer is generally referred to as a FREE layer, having a role of storing information. There is presently obtained a certain type of MTJ element that exhibits an MR ratio as the resistance variation ratio in excess of 50%, which type is becoming a main target of the developments of MRAMs.
Data can be written into an MRAM using an MTJ element by inverting the magnetization direction of the above-mentioned FREE layer by flowing at least a constant current through a bit line and a word line which are orthogonal to each other over each memory cell to thereby control that magnetization direction of the FREE layer with the magnitude of a resultantly occurring synthetic magnetic field.
On the other hand, data can be read out from it by applying a voltage between the two magnetic films of an MTJ element that corresponds to a selected bit to thereby read out the value of resistance from a resultantly flowing current or by flowing a constant current through the selected MTJ element to thereby read out a resultantly occurring voltage between these two magnetic films.
One example of the MRAMs using such an MTJ element uses two MOS transistors and two MTJ elements to represent one-bit data and is reported in a literature of, for example, “A 10-ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell” in a digest of Technical Paper, p. 128, of ISSC C2000. The MRAM reported in this literature, however, constitutes one-bit data of two MOS transistors and two MTJ elements as described above and so finds it difficult to provide a mass-capacity memory.
On the contrary, such a method is proposed (see, for example, Jpn. Pat. Appln. No. 2001-390518) as to manufacture another example of MRAM using an MTJ element in which, as shown in FIG. 1, a selection MOS transistor SG1 is shared in use by a plurality of memory cells MC1 through MC4 to enable reducing the cell area, thus contributing to an increase in integration density.
The MRAM according to this proposed method has such a cell cross section as shown in FIG. 2, for example. On a semiconductor substrate 101 are there arranged a gate wiring line RSW1 of the selection MOS transistor SG1 and a select line SL1 which is connected to a diffusion layer 102 of the selection MOS transistor SG1. Furthermore, above the select line SL1 are there arranged a write-in bit line WBL1 and a sub-bit line SBL1. On the sub-bit line SBL1 are there arranged MTJ elements MTJ1 through MTJ4 which constitute memory cells MC1 though MC4 respectively.
The MRAM having a structure shown in FIG. 2 has such a wiring configuration that the write-in bit line WBL1 is physically separated from the MTJ elements. The write-in bit line WBL1 has a role of generating two magnetic fields having different directions in order to determine the alignment of a FREE layer of the MTJ element, so that the physical separation of the write-in bit line WBL1 and the MTJ elements may give rise to a suspected a decrease in intensity of an easy-axis directional write-in magnetic field applied on the MTJ elements, which is a key to information storage. Therefore, to solve it, a bit line current must be increased, thus leading to a problem of an increase in current dissipation.